1. Field of the Invention
This invention relates to the field of power switch driver circuits, and particularly to driver circuits designed to prevent cross conduction between a pair of series-connected power switches.
2. Description of the Related Art
Many circuits include an output stage consisting of two power switches connected in series, with each switch conducting a respective current to or from a common node which serves as the stage's output. The switches are typically connected between a supply voltage and ground; as such, it is important that only one switch be closed at a time, to prevent “shoot-through” currents from flowing through both switches.
A number of “anti-cross conduction” techniques have been developed to ensure that both switches are not closed at the same time. A typical approach is shown in FIG. 1. A pair of power switches, here first and second field-effect transistors (FETs) Q1 and Q2, have their current circuits connected in series between a supply voltage VCC and ground. “High-side” transistor Q1 and “low-side” transistor Q2 are connected together at a common node 10, which provides the stage's output OUT. The transistors are controlled with respective control signals DRVH and DRVL provided by high-side and low-side driver circuits 12 and 14, respectively. Q1 conducts a current to node 10 when driven on by DRVH, and Q2 conducts a current from node 10 when driven on by DRVL. An input signal IN is provided to control the switches: when “high”, Q1 is to be driven on (and Q2 is to be off), and when “low”, Q2 is to be driven on (and Q1 is to be off).
To prevent both Q1 and Q2 from being on simultaneously, the driver circuit may employ an anti-cross conduction technique. This typically involves using drive signals DRVH and DRVL as feedback signals that serve as “lockout” signals for the opposite driver. For example, in FIG. 1, the input signal IN and its complement IN are provided to respective logic gates 16 and 18, along with respective lockout signals Llock and Hlock; the outputs of gates 16 and 18 are provided to driver circuits 12 and 14, respectively. Lockout signals Hlock and Llock are provided by respective comparators 20 and 22: comparator 20 receives DRVH and a reference voltage REF at respective inputs, and its output Hlock goes low when DRVH>REF. Similarly, comparator 22 receives DRVL and REF at respective inputs, and its output Llock goes low when DRVL>REF. In this way, when DRVH is high and Q1 is on, Hlock is low and IN is locked out by gate 18, which keeps DRVL low and Q2 off. When DRVL is high and Q2 is on, Llock is low and IN is locked out, keeping DRVH low and Q1 off.
This approach works well for most circumstances, but may be unreliable for input events having intervals shorter than the settling time of the feedback loop. A narrow pulse on IN, for example, may begin to propagate through driver circuit 12, and then propagate through driver circuit 14 when the pulse falls. If the propagation delay through driver circuit 12 is longer than the pulse width, a race condition may arise that results in both Q1 and Q2 being on at the same time. This is referred to as “cross-conduction”, which results in shoot-through currents that consume excessive current and can damage the power devices.